EEPROMs are non-volatile memory devices which are erased and programmed using electrical signals. Within an EEPROM device are a plurality of memory cells, each of which may be individually programmed and erased. In general, each EEPROM cell has two transistors. As an example, a FLOTOX (floating gate-tunnel oxide) EEPROM cell includes a floating gate transistor and a select transistor. The select transistors in an EEPROM device are used to select individual EEPROM cells which are to be erased or programmed. The floating gate transistors in the device are those transistors which actually perform the erase and program operations in the individual cells. To program and erase a cell, a phenomenon known as electron tunneling is used to store either a positive or a negative charge, respectively, on a floating gate electrode of the floating gate transistor. Programming is accomplished by applying a positive voltage to a drain of the floating gate transistor while a control gate is held at ground. As a result, electrons tunnel from the floating gate of the transistor through a tunnel dielectric to the drain, leaving the floating gate positively charged. An EEPROM cell is erased by storing negative charge on the floating gate. Negative charge storage on the floating gate is generally achieved by applying a positive voltage to the control gate of the transistor while grounding the drain and source. Such a bias causes electrons to tunnel from the drain through the tunnel dielectric to the floating gate, creating a negative charge on the floating gate.
In order to maximize the performance of an EEPROM device, program and erase times must be kept to a minimum. To improve program and erase speeds, it is important to maximize a parameter known as the capacitance coupling ratio, or the coupling coefficient. The capacitance coupling ratio is defined as: ##EQU1## In the above equation, K.sub.cr is the coupling coefficient, C1 is the capacitance between the control gate and the floating gate of the floating gate transistor, and C2 is the capacitance between the floating gate and the substrate. Maximizing the capacitance coupling ratio implies maximizing the voltage which appears across the tunnel dielectric during programming and erasing operations, which in turn implies minimizing the time required to charge the floating gate. As an example of how the capacitance coupling ratio affects EEPROM cell operation, a capacitance coupling ratio in which K.sub.cr =0.70 implies that during an erase operation in which 18 volts is applied to the drain, only 70% of the 18 volts (i.e. 12.6 volts) is transferred across the tunneling dielectric. As the coupling ratio increases, a higher voltage appears across the tunnel dielectric, resulting in shorter charge times. Therefore, erase and programming times can be reduced if K.sub.cr if maximized.
In order to maximize the capacitance coupling ratio, EEPROM manufacturers generally try to minimize the area of the tunnel dielectric through which electrons travel, hereinafter referred to as the tunnel area. By making the tunnel area smaller, the capacitance between the floating gate and the substrate, C2 in the above equation, is reduced, thereby increasing K.sub.cr. One common approach to forming the smallest tunnel area possible is to lithographically define a portion of a dielectric layer through which electrons will travel. In many EEPROM devices, a gate dielectric layer on the order of 200-400 .ANG. (20-40 nm) exists between a floating gate and an underlying channel region. Because such dielectric thicknesses generally prohibit electron tunneling at normal operation voltages, but are otherwise necessary for adequate electrical isolation, a portion of the gate dielectric layer must be made thinner. Thinning of the gate dielectric layer typically occurs by etching a portion of the gate dielectric which is defined by a tunnel opening, also known as a tunnel window, to expose a channel region. A very thin tunnel dielectric, on the order of 50-100 .ANG. (5-10 nm), is then grown or deposited on the exposed portion of the channel, thereby establishing the tunnel area. Using this process, a tunnel area can theoretically be made as small as the resolution limit of lithographic equipment used to define the tunnel opening. For example, lithography equipment having a minimum resolution of 0.8 .mu.m will, in best case, result in a minimum tunnel area of 0.8 .mu.m.times.0.8 .mu.m.
While an EEPROM manufacturer may be able to successfully pattern a tunnel opening having dimensions equal to the lowest lithographic resolution limit, transferring the tunnel opening pattern into an actual opening in the gate dielectric is a challenge. In particular, it is very difficult to control a dielectric etch process which etches an opening of such small area. Typically, dry etches are very controllable and would be suitable for use in defining a tunnel area in an EEPROM device, except that dry etches tend to damage the channel region within a substrate. For this reason, most manufacturers prefer to use a less controllable, but less damaging, wet etch. However, due to the inability to tightly control the wet etch process, a tunnel opening which is lithographically defined as 0.8 .mu.m.times.0.8 .mu.m may translate into a 0.9 .mu.m.times.0.9 .mu.m opening in the gate dielectric. Another manufacturing problem associated with known EEPROM devices is that of ensuring repeatability in tunnel opening size from cell to cell and from device to device. A consistent tunnel area is essential in establishing a uniform level of EEPROM device performance. Yet another problem is that alignment of the tunnel opening is very critical. Therefore, to reduce chances of misalignments, many manufacturers include misalignment tolerances in the device layout. Unfortunately, these built-in tolerances undesirably increase the overall device size and undesirably increase floating gate-to-substrate capacitance, C2, due to an increase in the size of the active area beneath the floating gate.